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High-speed ADCs (≥10 MSPS)

ADS62C17

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Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS62C17

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1081 Architecture Pipeline SNR (dB) 67 ENOB (Bits) 10.8 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 200 Resolution (Bits) 11 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1081 Architecture Pipeline SNR (dB) 67 ENOB (Bits) 10.8 SFDR (dB) 85 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 200 MSPS
  • 11-bit Resolution with No Missing Codes
  • 90 dBc SFDR at Fin = 10 MHz
  • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
    using TI proprietary SNRBoost technology
  • Total Power 1.1 W at 200 MSPS
  • 90 dB Cross-talk
  • Double Data Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Gain Tuning Capability in Fine Steps (0.001 dB)
    Allows Channel-to-channel Gain Matching
  • Supports Input Clock Amplitude Down to
    400 mV p-p Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)
  • Maximum Sample Rate: 200 MSPS
  • 11-bit Resolution with No Missing Codes
  • 90 dBc SFDR at Fin = 10 MHz
  • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW
    using TI proprietary SNRBoost technology
  • Total Power 1.1 W at 200 MSPS
  • 90 dB Cross-talk
  • Double Data Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Gain Tuning Capability in Fine Steps (0.001 dB)
    Allows Channel-to-channel Gain Matching
  • Supports Input Clock Amplitude Down to
    400 mV p-p Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet (Rev. A) 17 Jul 2009
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide TSW4200 Demonstration Kit User's Guide (Rev. C) 31 Oct 2012
Application note Understanding Low-Amplitude Behavior of 11-bit ADCs 22 Oct 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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Support software

HSADC-SPI-UTILITY — ADS5400 EVM GUI

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Support software

SBAC120 — TIGAR Support Files

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Simulation model

ADS61xx, ADS62Pxx HS IBIS Model (Rev. B)

SLWC088B.ZIP (653 KB) - IBIS Model
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Simulation model

ADS62C17 TINA-TI Transient Reference Design

SBAM016.TSC (106 KB) - TINA-TI Reference Design
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Simulation model

ADS62C17 TINA-TI Transient Spice Model

SBAM015.TSM (14 KB) - TINA-TI Spice Model
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Calculation tool

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware
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Calculation tool

JITTER-SNR-CALC — Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

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Supported products & hardware
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Design tool

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Supported products & hardware

Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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