)ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.
ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up.
ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 12Bits 80MSPS ADC with Buffered Analog Inputs datasheet | Feb 7, 2008 | |
| Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | May 22, 2015 | ||
| Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | Jul 19, 2013 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | Sep 10, 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | Apr 28, 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | Sep 4, 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | Jun 8, 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | Jun 2, 2008 | ||
| Application note | QFN Layout Guidelines | Jul 28, 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
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