The AFE7950 is a high performance, wide bandwidth multi-channel transceiver, integrating four RF sampling transmitter chains, four RF sampling receiver chains and two RF sampling feedback chains (six RF sampling ADCs total). With operation up to 12 GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.
The TX signal paths support interpolation and digital up conversion options that deliver up to 1200MHz of signal bandwidth for four TX or 2400MHz for two TX. The output of the DUCs drives a 12GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1dB analog and 0.125dB digital steps.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each).
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The AFE7950 family evaluation module (EVM) is a flexible RF-sampling transceiver platform that can be configured to support up to four-transmit, four-receive, and two-feedback (4T4R+2FB) channels simultaneously. The EVM interfaces with the TI pattern/capture card solution shown below (sold (...)
The TRF-LSC-AFE7950EVM evaluation module is used to evaluate the performance of TI's AFE79xx family of integrated RF sampling transceivers with TI's TRF1208 single-ended-to-differential amplifier on RX, and TRF1108 differential-to-single-ended amplifier on TX. The AFE79xx devices support up to four (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCBGA (ALK) | 400 | Ultra Librarian |
| FCBGA (ABJ) | 400 | Ultra Librarian |
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