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The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.
The ADS8365 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 16-Bit, 250kSPS 6-Channel Simultaneous Sampling SAR Analog-to-Digital Converters datasheet (Rev. C) | Mar 27, 2008 | |
| White paper | Voltage-reference impact on total harmonic distortion | Aug 1, 2016 | ||
| E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | May 21, 2015 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | Mar 17, 2011 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | Nov 10, 2010 | ||
| More literature | ADS8365EVM Readme Page Thank You Letter (Rev. A) | Dec 5, 2006 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADS8365M-EVM is designed for the prototyping and evaluation of the ADS8365 analog-to-digital converter (ADC). This high-resolution, 16 bit, parallel analog-to-digital, 250 kHz, SAR device, can be configured as a single or fully differential, pseudo-bipolar input. The EVM uses a (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
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