The ADS8505 is a complete 16-bit sampling A/D converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, SAR A/D with S/H, reference, clock, interface for microprocessor use, and 3-state output drivers.
The ADS8505 is specified at a 250-kHz sampling rate over the full temperature range. Precision resistors provide an industry standard ±10-V input range, while the innovative design allows operation from a single +5-V supply, with power dissipation under 100 mW.
The ADS8505 is available in 28-pin SOIC and 28-pin SSOP packages, both fully specified for operation over the industrial -40°C to 85°C temperature range.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | 16-Bit 250-KSPS Sampling CMOS Analog-to-Digital Converter datasheet (Rev. B) | Feb 1, 2007 | |
| White paper | Voltage-reference impact on total harmonic distortion | Aug 1, 2016 | ||
| E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | May 21, 2015 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | Mar 17, 2011 | ||
| Application note | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | Nov 10, 2010 | ||
| Application note | Upgrading from the ADS7804/05 to the ADS8504/05 | Apr 30, 2007 | ||
| Application note | Controlling the ADS7805 With TMS320 Series DSPs | Nov 9, 2004 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADS8505EVM is designed for the prototyping and evaluation of the ADS8505 analog-to-digital converter (ADC). This 16-bit, capacitor-based, SAR/ADC operates at a maximum rate of 250 KSPS. The EVM allows the use of an optional buffer amplifier U8 to condition the input signals to the ADS8505 (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SSOP (DB) | 28 | Ultra Librarian |
| SOIC (DW) | 28 | Ultra Librarian |
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