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Latest version
Version: 1.0.0
Release date: 07 Nov 2024
Precision ADCs
Example FPGA code for ADS127L18 data port
This is an example of how to latch data from the ADS127L18 frame-sync data port that outputs the channel conversion data. The data port is a synchronous, read-only interface with synchronized output clock signals (FSYNC and DCLK) and channel data (DOUTx). This Verilog module captures and splits the continuous 1/2/4/8 lane data (including STATUS and CRC bytes if enabled) into eight separate channels and latches the data between frames.
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Latest version
Version: 1.0.0
Release date: 14 Jan 2025
Precision ADCs
Example C code for MSPM0 + ADS127L18
Prototype your microcontroller solution for interfacing with the ADS127L18 product family. This example code project uses the MSPM0 to configure the ADS127L18 EVM and record conversion via an SPI peripheral.