PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The LMK1C110xA is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.
All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.
The LMK1C110xA supports a asynchronous output enable control (1G) which switches the outputs into a low state when 1G is low. Asynchronous enable and disable is helpful for 1PPS applications and DC inputs operations. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LMK1C110xA 1.8V, 2.5V, and 3.3V Low Noise Asynchronous LVCMOS Clock Buffer Family datasheet | PDF | HTML | 27 May 2025 |
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PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.