Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

LMK1C1102

ACTIVE

2-channel output LVCMOS 1.8-V buffer

Order now
Data sheet

LMK1C1102

ACTIVE
Data sheet Order now

Product details

Number of outputs 2 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
Number of outputs 2 Additive RMS jitter (typ) (fs) 19.2 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 25 Operating temperature range (°C) -40 to 125 Rating Catalog Output type LVCMOS Input type LVCMOS
TSSOP (PW) 8 19.2 mm² (3 mm × 6.4 mm) WSON (DQF) 8 4 mm² (2 mm × 2 mm)
  • High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
  • Very low output skew < 50 ps
  • Extremely low additive jitter < 50 fs maximum
    • 7.5 fs typical at VDD = 3.3 V
    • 10 fs typical at VDD = 2.5 V
    • 19.2 fs typical at VDD = 1.8 V
  • Very low propagation delay < 3 ns
  • Synchronous output enable
  • Supply voltage: 3.3 V, 2.5 V, or 1.8 V
    • 3.3-V tolerant input at all supply voltages
    • Fail-safe inputs
  • fmax = 250 MHz for 3.3 V fmax = 200 MHz for 2.5 V and 1.8 V
  • Operating temperature range: –40°C to 125°C
  • Available in 8-pin TSSOP package
  • Available in 8-pin WSON package
  • High-performance 1:2, 1:3 or 1:4 LVCMOS clock buffer
  • Very low output skew < 50 ps
  • Extremely low additive jitter < 50 fs maximum
    • 7.5 fs typical at VDD = 3.3 V
    • 10 fs typical at VDD = 2.5 V
    • 19.2 fs typical at VDD = 1.8 V
  • Very low propagation delay < 3 ns
  • Synchronous output enable
  • Supply voltage: 3.3 V, 2.5 V, or 1.8 V
    • 3.3-V tolerant input at all supply voltages
    • Fail-safe inputs
  • fmax = 250 MHz for 3.3 V fmax = 200 MHz for 2.5 V and 1.8 V
  • Operating temperature range: –40°C to 125°C
  • Available in 8-pin TSSOP package
  • Available in 8-pin WSON package

The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.

The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Three different fan-out variations, 1:2, 1:3, 1:4, are available.

All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.

All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.

The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.
filter Find other Clock buffers
Download View video with transcript Video

Technical documentation

No results found. Please clear your search and try again.
View all 3
Top documentation Type Title Format options Date
* Data sheet LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family datasheet (Rev. D) PDF | HTML Feb 18, 2022
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML Sep 3, 2024
Application note LMK1C110x Key Performance in System Level (Rev. A) Mar 10, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK1C1104DFNEVM — LMK1C1104 low jitter 1:4 LVCMOS fan-out buffer DFN evaluation module

LMK1C1104DQF is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, four LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1104DQF. LMK1C1104DFNEVM is equipped with (...)
User guide: PDF | HTML
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Evaluation board

LMK1C1104EVM — LMK1C1104 low jitter 1:4 LVCMOS fan-out buffer evaluation module

LMK1C1104 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, four LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1104, however, this EVM can also be used to evaluate (...)
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Evaluation board

LMK1C1108EVM — LMK1C1108 low jitter 1:8 LVCMOS fan-out buffer evaluation module

LMK1C1108 is a high-performance, low additive jitter LVCMOS clock buffer with one LVCMOS input, eight LVCMOS outputs, and a global output enable pin. This evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1C1108. This EVM can also be used to evaluate other (...)
User guide: PDF | HTML
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

Supported products & hardware
Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 8 Ultra Librarian
WSON (DQF) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos