DS90UR905Q-Q1
- 5- to
65-MHz PCLK support (140 Mbps to
1.82 Gbps) - AC-Coupled STP interconnect cable up to 10 meters
- Integrated terminations on serializer and deserializer
- At speed link BIST mode and reporting pin
- Optional I2C-compatible serial control bus
- RGB888 + VS, HS, DE support
- Power down mode minimizes power dissipation
- 1.8-V or 3.3-V compatible LVCMOS I/O interface
- Automotive-grade product: AEC-Q100 grade 2 qualified
- >8-kV HBM and ISO 10605 ESD rating
- Backward compatible mode for operation with older generation devices
- SERIALIZER —
DS90UR905Q-Q1
- RGB888 + VS/HS/DE serialized to 1 Pair FPD-Link II
- Randomizer/scrambler — DC-balanced data stream
- Selectable output VOD and adjustable de-emphasis
- DESERIALIZER —
DS90UR906Q-Q1
- FAST random data lock; no reference clock required
- Adjustable input receiver equalization
- LOCK (real time link status) reporting pin
- EMI minimization on output parallel bus (SSCG)
- Output slew control (OS)
The DS90UR90xQ-Q1 chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight, cost, and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock, balances the data payload, and level
shifts the signals to high-speed, low voltage differential signaling. Up to 24 inputs are
serialized, along with the three video control signals. This supports full
24-bit color or 18-bit color and 6 general-purpose signals (for example, Audio I2S
applications).
The DS90UR906Q-Q1 deserializer recovers the data (RGB) and control signals and extracts the clock from the serial stream. The DS90UR906Q-Q1 is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.
Serial transmission is optimized by a user-selectable de-emphasis, differential output level select features, and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The deserializer may be configured to generate spread spectrum clock and data on its parallel outputs.
The DS90UR905Q-Q1 serializer is offered in a 48-pin WQFN and the DS90UR906Q-Q1 (deserializer) is offered in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of –40°C to +105°C.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90UR90xQ-Q1 5- to 65-MHz, 24-bit Color FPD-Link II Serializer and Deserializer datasheet (Rev. I) | PDF | HTML | 2019/10/3 | ||
| 應用說明 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/4/29 | ||||
| 應用說明 | Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) | 2013/4/26 | ||||
| 應用說明 | AN-1807 FPD-Link II Display SerDes Overview (Rev. B) | 2013/4/26 | ||||
| 使用指南 | DVI - FPD LINK II (DS90UR905Q/906Q) Demo Platform User Guide | 2012/6/15 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
訂購與品質
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