SN74CBTLV3245A-Q1

現行

產品詳細資料

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm)
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results: –
    • Device Temperature Grade 1: –40°C to +125°C
    • Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
  • Standard ’245-Type Pinout
  • 5-Ω Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results: –
    • Device Temperature Grade 1: –40°C to +125°C
    • Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
  • Standard ’245-Type Pinout
  • 5-Ω Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)

The SN74CBTLV3245A-Q1 provides eight bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maitains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE is tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3245A-Q1 provides eight bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maitains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE is tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 2
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CBTLV3245A-Q1 Low-Voltage Octal FET Bus Switch datasheet PDF | HTML 2026/1/16
功能安全資訊 SN74CBTLV3245A-Q1 Functional Safety FIT Rate, FMD and Pin FMA PDF | HTML 2026/7/27

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RKS) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片