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UCC21225A

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Data sheet

UCC21225A

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Isolation rating Basic Power switch GaNFET, IGBT, MOSFET, SiCFET Withstand isolation voltage (VISO) (Vrms) 2500 Working isolation voltage (VIOWM) (Vrms) 792 Transient isolation voltage (VIOTM) (VPK) 3535 Peak output current (source) (typ) (A) 4 Peak output current (sink) (typ) (A) 6 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 6.5 Output VCC/VDD (max) (V) 25 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 18 Propagation delay time (µs) 0.019 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Rise time (ns) 6 Fall time (ns) 7 Undervoltage lockout (typ) (V) 5
Number of channels 2 Isolation rating Basic Power switch GaNFET, IGBT, MOSFET, SiCFET Withstand isolation voltage (VISO) (Vrms) 2500 Working isolation voltage (VIOWM) (Vrms) 792 Transient isolation voltage (VIOTM) (VPK) 3535 Peak output current (source) (typ) (A) 4 Peak output current (sink) (typ) (A) 6 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 6.5 Output VCC/VDD (max) (V) 25 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 18 Propagation delay time (µs) 0.019 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Rise time (ns) 6 Fall time (ns) 7 Undervoltage lockout (typ) (V) 5
VLGA (NPL) 13 25 mm² (5 mm × 5 mm)
  • Universal: dual low-side, dual high-side or half-bridge driver
  • 5 × 5mm, space-saving LGA-13 package
  • Switching parameters:
    • Typical propagation delay: 19ns
    • Maximum delay matching: 5ns
    • Maximum pulse-width distortion: 6ns
  • CMTI greater than 100V/ns
  • 4A peak source, 6A peak sink output
  • TTL and CMOS compatible inputs
  • Input VCCI range: 3V to 18V
  • Up to 25V VDD with 5V UVLO
  • Programmable overlap and dead time
  • Rejects input transients shorter than 5ns
  • Fast disable for power sequencing
  • Safety-related certifications:
    • 3535VPK isolation per DIN V VDE V 0884-11:2017-01
    • 2500VRMS isolation for 1 minute per UL 1577
    • CQC per GB 4943.1-2022
  • Universal: dual low-side, dual high-side or half-bridge driver
  • 5 × 5mm, space-saving LGA-13 package
  • Switching parameters:
    • Typical propagation delay: 19ns
    • Maximum delay matching: 5ns
    • Maximum pulse-width distortion: 6ns
  • CMTI greater than 100V/ns
  • 4A peak source, 6A peak sink output
  • TTL and CMOS compatible inputs
  • Input VCCI range: 3V to 18V
  • Up to 25V VDD with 5V UVLO
  • Programmable overlap and dead time
  • Rejects input transients shorter than 5ns
  • Fast disable for power sequencing
  • Safety-related certifications:
    • 3535VPK isolation per DIN V VDE V 0884-11:2017-01
    • 2500VRMS isolation for 1 minute per UL 1577
    • CQC per GB 4943.1-2022

The UCC21225A is an isolated dual-channel gate driver with 4A source and 6A sink peak current in a 5mm × 5mm LGA-13 package. UCC21225A is designed to drive power transistors up to 5MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 2.5kVRMS isolation barrier, with 100V/ns minimum common-mode transient immunity (CMTI). Internal functional isolation between the two secondary side drivers allows working voltage up to 700VDC.

Configure this driver as two low-side, two high-side, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded.

The device accepts VDD supply voltages up to 25V. A wide input VCCI range from 3V to 18V makes the driver an excellent choice for interfacing with both analog and digital controllers. All the supply voltage pins have undervoltage lock-out (UVLO) protection.

With all these advanced features, the UCC21225A enables high power density, high efficiency, and robustness in a wide variety of power applications.

The UCC21225A is an isolated dual-channel gate driver with 4A source and 6A sink peak current in a 5mm × 5mm LGA-13 package. UCC21225A is designed to drive power transistors up to 5MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 2.5kVRMS isolation barrier, with 100V/ns minimum common-mode transient immunity (CMTI). Internal functional isolation between the two secondary side drivers allows working voltage up to 700VDC.

Configure this driver as two low-side, two high-side, or a half-bridge driver with programmable dead time (DT). A disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded.

The device accepts VDD supply voltages up to 25V. A wide input VCCI range from 3V to 18V makes the driver an excellent choice for interfacing with both analog and digital controllers. All the supply voltage pins have undervoltage lock-out (UVLO) protection.

With all these advanced features, the UCC21225A enables high power density, high efficiency, and robustness in a wide variety of power applications.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet UCC21225A 4A, 6A, 2.5kVRMS Isolated Dual-Channel Gate Driver in LGA datasheet (Rev. B) PDF | HTML Nov 9, 2026
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. AB) Oct 2, 2026
Certificate UCC2x225 CQC Certificate (NPL Package - TAI) (Rev. A) Aug 15, 2023
Application brief External Gate Resistor Selection Guide (Rev. A) Feb 28, 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) Feb 28, 2020
Application brief How to Drive High Voltage GaN FETs with UCC21220A Mar 6, 2019
Certificate UL Certification E181974 Vol 4. Sec 8 (Rev. A) Jul 23, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21225AEVM-365 — UCC21225A 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module

UCC21225AEVM-365 is designed for evaluating UCC21225ANPL, which is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current capability in a 5x5 LGA package. This EVM can be used as a reference design for driving power MOSFETs, IGBTs, and SiC MOSFETs with UCC21225A pin (...)
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Simulation model

UCC21225A PSpice Transient Model

SLUM574.ZIP (55 KB) - PSpice model
Supported products & hardware
Simulation model

UCC21225A Unencrypted PSpice Transient Model

SLUM575.ZIP (4 KB) - PSpice model
Supported products & hardware
Reference design

PMP20587 — Inverting buck-boost reference design

This reference design uses UCD3138064A as a digital controller to control two-phase two-rail inverting buck-boost. This non-isolated converter is used for wireless radio power. The input voltage is from -35 V to -60 V. There are two outputs. The default output voltage of rail 1 is 32 V and max (...)
Supported products & hardware
Reference design

PMP21943 — 48-V / 25-A negative-to-positive synchronous buck-boost reference design for power amplifiers

This reference design is a negative-to-positive synchronous buck-boost converter for power amplifier applications. The circuit is powered from the nominal -48-V system source to provide an output voltage of +48 V at 25 A. The design uses two dual synchronous boost controllers for 4-phase operation (...)
Supported products & hardware
Reference design

PMP23332 — Interleaved and multiphase inverting buck-boost converter reference design

This reference design uses the UCD3138064A as a digital controller to control inverting buck-boost with the capability of supporting two-phase peak current mode control. The soft-switching technology is used in this design to improve the power efficiency. The input voltage range is -62 V to -36 V. (...)

Supported products & hardware
Reference design

PMP23475 — GaN-based 5kW two-phase totem-pole PFC reference design with zero current detection

This reference design is a high-density and high-efficiency, 5kW power factor correction (PFC) converter implemented with TI high-performance Gallium Nitride (GaN) power switches. A peak system efficiency of 99.2% with an open-frame power density of 120W/in3 was measured. The power stage uses a (...)
Supported products & hardware
Reference design

PMP40988 — Variable-frequency, ZVS, 5-kW, GaN-based, two-phase totem-pole PFC reference design

This reference design is a high-density and high-efficiency 5-kW totem-pole power factor correction (PFC) design. The design uses a two-phase totem-pole PFC operating with variable frequency and zero voltage switching (ZVS). The control uses a new topology and improved triangular current mode (...)
Supported products & hardware
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VLGA (NPL) 13 Ultra Librarian
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