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SN74LVC1G08

ACTIVE

1-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

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Data sheet

SN74LVC1G08

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
X2SON (DSF) 6 1 mm² (1 mm × 1 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) DSBGA (YZP) 5 2.1875 mm² (— mm × — mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC1G08 Single 2-Input Positive-AND Gate datasheet (Rev. Z) PDF | HTML Mar 26, 2019
Selection guide Logic Guide (Rev. AC) PDF | HTML Nov 13, 2025
Product overview Generate an Enable Signal that can be Toggled PDF | HTML Jun 14, 2023
Application brief Optimizing Optical Network Terminal Units With Logic PDF | HTML Apr 5, 2023
Application brief Optimizing Industrial Robot CPU Boards with Logic and Voltage Translation PDF | HTML Dec 12, 2022
Application brief Optimizing WLAN and WiFi Access Point Systems With Logic and Voltage Translation PDF | HTML Nov 3, 2022
Application note Applications of Logic and Translation in IP Cameras (Rev. A) PDF | HTML Mar 29, 2021
Application note Optimizing HVAC Gateway Designs W/ Common Logic & Translation Voltage Use Cases (Rev. B) PDF | HTML Mar 29, 2021
Application brief Simplifying Solid-State Relay Designs With Logic PDF | HTML Jan 8, 2021
Application brief Enable and Disable Digital Signals PDF | HTML Nov 4, 2020
Application brief Combine Power Good Signals PDF | HTML Oct 2, 2020
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017

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Simulation model

SN74LVC1G08 Behavioral SPICE Model

SCEM642.ZIP (7 KB) - PSpice model
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Simulation model

SN74LVC1G08 IBIS Model (Rev. A)

SCEM167A.ZIP (42 KB) - IBIS model
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Many TI reference designs include the SN74LVC1G08

Use our reference design selection tool to review and identify designs that best match your application and parameters.
Package Pins CAD symbols, footprints & 3D models
X2SON (DSF) 6 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
DSBGA (YZP) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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