ホーム インターフェイス 高速 SerDes FPD-Link SerDes

DS90UH925AQ-Q1

アクティブ

製品詳細

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP Signal conditioning Adaptive Equalizer EMI reduction SSC Compatible Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP Signal conditioning Adaptive Equalizer EMI reduction SSC Compatible Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • Integrated HDCP Cipher Engine with On-chip Key Storage
  • Bidirectional Control Interface Channel Interface with I2C
    Compatible Serial Control Bus
  • Supports High Definition (720p) Digital Video Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 – 85 MHz PCLK Supported
  • Single 3.3 V Operation with 1.8 V or 3.3 V Compatible
    LVCMOS I/O Interface
  • AC-coupled STP Interconnect up to 10 meters
  • Parallel LVCMOS Video Inputs
  • DC-balanced & Scrambled Data with Embedded Clock
  • Supports HDCP Repeater Application
  • Dedicated Interrupt Pin for Remote Interrupts
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD rating
  • Backward Compatible Modes
  • Integrated HDCP Cipher Engine with On-chip Key Storage
  • Bidirectional Control Interface Channel Interface with I2C
    Compatible Serial Control Bus
  • Supports High Definition (720p) Digital Video Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 – 85 MHz PCLK Supported
  • Single 3.3 V Operation with 1.8 V or 3.3 V Compatible
    LVCMOS I/O Interface
  • AC-coupled STP Interconnect up to 10 meters
  • Parallel LVCMOS Video Inputs
  • DC-balanced & Scrambled Data with Embedded Clock
  • Supports HDCP Repeater Application
  • Dedicated Interrupt Pin for Remote Interrupts
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD rating
  • Backward Compatible Modes

The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.

EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.

Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin.

The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.

EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.

Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin.

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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート DS90UH925AQ-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP データシート 2014/01/23

設計と開発

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アプリケーション・ソフトウェアとフレームワーク

ALP — Analog LaunchPad Framework Utility

To get started with Analog LaunchPad (ALP) software: Download and install the ALP Framework Utility. Add new device profiles and example scripts with the ALP-PROFILE-UPDATE tool.
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サポート・ソフトウェア

ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software

ALP Profile Update contains latest fixes and updates to ALP profiles. If you are installing for the first time please install ALP Profile Update after installing ALP Framework.
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シミュレーション・モデル

DS90UH925AQ IBIS Model

SNLM166.ZIP (68 KB) - IBIS モデル
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パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
WQFN (RHS) 48 Ultra Librarian

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