The TPS766 is a low-dropout (LDO) linear voltage regulator that supports an input voltage range from 2.5V to 16V (new chip) and up to 250mA of load current. For the new chip, the supported output range is from 1.2V to 12V (fixed version) or from 0.8V to 14.6V (adjustable version).
The input voltage range is up to 16V (new chip), which makes the device a good choice for operating from transformer secondary windings and regulated rails (such as 10V or 12V). Additionally, the wide output voltage range allows the device to generate the bias voltage for silicon carbide (SiC) gate drivers and microphones, as well as power microcontrollers (MCUs) and processors.
Wide bandwidth PSRR performance is greater than 70dB at 1kHz and 46dB at 1MHz (new chip), which helps attenuate the switching frequency of an upstream DC/DC converter and minimizes post regulator filtering. The new chip supports internal soft-start circuit mechanism that reduces inrush current during start-up, thus allowing for smaller input capacitance.
The legacy chip supports constant quiescent current across the complete load current range (typically 35µA for the full range of output current, 0mA to 250mA).
The TPS766 LDO also features a sleep mode, where applying a TTL high signal to EN (enable) shuts down the regulator. In disabled mode, the quiescent current for the legacy chip is less than 1µA (typ) and the quiescent current for the new chip is approximately 1.6µA (typ).
Power-good (PG) is an active-high output used to implement a power-on reset or a low-battery indicator.
For the fixed-output version, The TPS766 provides an output range of 1.5V to 5.0V (legacy chip) and 1.2V to 12V (new chip). For the adjustable version, program the output voltage over the range of 1.25V to 5.5V (legacy chip) and 0.8V to 14.6V (new chip). The TPS766 is available in an 8-pin SOIC package.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | TPS766 250mA, 16V, Low-Dropout Voltage Regulator datasheet (Rev. E) | PDF | HTML | Mar 15, 2024 |
| Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | Aug 18, 2020 | |
| Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | Aug 9, 2017 | |
| Analog design Journal | Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter | May 6, 2010 |
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
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