Home Logic & voltage translation Logic gates NAND gates
Home
Logic & voltage translation
Logic gates
NAND gates

SN74LVC2G132

ACTIVE

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Order now
Data sheet

SN74LVC2G132

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter Find other NAND gates
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device.
SN74AHC132 ACTIVE 4-ch 4-input 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA

Technical documentation

No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Data sheet Dual 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D) Dec 24, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Simulation model

SN74LVC2G132 Behavioral SPICE Model

SCEM617.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC2G132 IBIS Model (Rev. A)

SCEM411 (243 KB) - IBIS model
Supported products & hardware
Reference design

TIDA-010049 — TUV-assessed digital input reference design for IEC 61508 (SIL-2)

This 8-channel, group-isolated, digital input module reference design, focuses on applications with the need for industrial functional safety. This design has diagnostics implemented to help detect both permanent and transient random hardware faults. The concept of this input module has been (...)
Supported products & hardware
Reference design

TIDA-01487 — Isolated CAN Flexible Data (FD) Rate Repeater Reference Design

CAN and CANopen are legacy Fieldbus protocols used in many applications in factory automation. Whenever high voltage can damage the end equipment, there is need for isolation. This isolated CAN flexible data (FD) rate repeater reference design adds electrical isolation between two CAN (...)
Supported products & hardware
Reference design

TIDEP0046 — Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design

TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)

Supported products & hardware
Reference design

TIDEP0047 — Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)

Supported products & hardware
Reference design

TIDEP0076 — 3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light

The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC)  is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing (...)
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos