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SN74HCT74

ACTIVE

Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

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Data sheet

SN74HCT74

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 2 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm)
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible
  • Operating voltage range of 4.5 V to 5.5 V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40-µA max I CC
  • Typical t pd = 17 ns
  • ±4-mA output drive at 5 V
  • Low input current of 1 µA max
  • Inputs are TTL-voltage compatible

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
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SN74ACT74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
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SN74AHCT74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA
SN74LV2T74-EP ACTIVE Enhanced-product dual D-type flip-flops with clear, preset and integrated level shifter Voltage range 1.6V to 5.5V, average propagation delay 7ns, average drive strength 8mA
SN74LV2T74 ACTIVE 1.8-V to 5.5-V single power supply dual D-Type positive-edge-triggered flip-flops Voltage range 1.6V to 5.5V, average propagation delay 7ns, average drive strength 8mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flips With Clear and Preset datasheet (Rev. G) PDF | HTML Oct 21, 2022
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
PDIP (N) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
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