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SN74ACT74

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

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Data sheet

SN74ACT74

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 2 Technology family ACT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 90 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 20 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm)
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10.5ns at 5V
  • Inputs are TTL-voltage compatible
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10.5ns at 5V
  • Inputs are TTL-voltage compatible

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
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CD74HCT74 ACTIVE High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA
SN74AHCT74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops datasheet (Rev. J) PDF | HTML Apr 10, 2025
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
PDIP (N) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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