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CD74HCT74

ACTIVE

High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset

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Data sheet

CD74HCT74

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 2 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 25 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm)
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs
  • LSTTL input logic compatible
    • VIL(max) = 0.8 V, VIH(min) = 2 V
  • CMOS input logic compatible
    • II ≤ 1 µA at VOL, VOH
  • Buffered inputs
  • 4.5 V to 5.5 V operation
  • Wide operating temperature range: -55°C to +125°C
  • Supports fanout up to 10 LSTTL loads
  • Significant power reduction compared to LSTTL logic ICs

The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.

The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.
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CD74ACT74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
SN74AHCT74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet CD54HCT74, CD74HCT74 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger datasheet Aug 30, 2019
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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SOIC (D) 14 Ultra Librarian
PDIP (N) 14 Ultra Librarian
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