TAS5830
- Supports multiple output configurations
- 2 × 80W, BTL Mode(4Ω, 26V, THD+N=10%)
- 2 × 65W, BTL Mode(4Ω, 26V, THD+N=1%)
- 2 × 74W, BTL Mode(6Ω, 30V, THD+N=10%)
- 2 × 63W, BTL Mode(6Ω, 30V, THD+N=1%)
- 1 × 151W, PBTL Mode(3Ω, 30V, THD+N=10%)
- 1 × 131W, PBTL Mode(3Ω, 30V, THD+N=1%)
- Flexible audio I/O:
- Supports 32, 44.1, 48, 88.2, 96, 192kHz sample rates
- I2S, LJ, RJ, 4- 16 channels TDM input
- SDOUT for audio monitoring, sub-channel, or echo cancellation
- Supports 3-wire digital audio interface (no MCLK required)
- High-efficiency Class-D modulation
- > 90% power efficiency, 70mΩ RDSon
- Excellent audio performance:
- THD+N ≤ 0.03% at 1 W, 1kHz, PVDD = 12V
- SNR ≥ 110dB (A-weighted), ICN ≤ 40µVrms
- Flexible processing features
- 3-Band advanced DRC + 2 EQs + AGL + 2 EQs
- 15 BQs per channel, level meter
- 96kHz, 192kHz processor sampling
- Mixer, volume, dynamic EQ, output crossbar
- PVDD sensing and Class-H algorithm audio signal tracking
- Rattle suppression, Frequency limiter
- Flexible power supply configurations
- PVDD: 4.5V to 30V
- DVDD and I/O: 1.8V or 3.3V
- Excellent integrated self-protection:
- Over-current error (OCE)
- Cycle-by-cycle current limit supports 4 selectable OC levels
- Over-temperature warning (OTW)
- Over-temperature error (OTE)
- Under and over-voltage lock-out (UVLO/OVLO)
- PVDD voltage drop detection
- Easy system integration
- I2C Software Control (TAS5830 supports both Fast and Fast Plus mode) or Hardware Mode
- Fewer passives required compared to open-loop devices
The TAS5830 is a stereo high-performance, closed-loop Class-D with integrated audio processor and up to 192kHz audio support.
When setting the device into Hardware control mode, TAS5830 supports selecting switching frequency, analog gain, BTL/PBTL mode and cycle by cycle current limit threshold through pin configuration. This mode is designed to eliminate end system software driver integration efforts.
The TAS5830 also provides the DSP features Rattle suppression and Frequency limiter. Rattle suppression reduces the gain of the signal at frequencies that cause rattle through interaction with the speaker enclosure, improving sound quality. The frequency limiter process senses the input level, limits the gain of EQ dynamically and helps SPL without phase change.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | TAS5830 65W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Amplifier with Class-H Algorithm 数据表 | PDF | HTML | 2025年 5月 20日 | ||
EVM 用户指南 | TAS5830 Evaluation Module | PDF | HTML | 2025年 5月 2日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
TAS5830EVM — TAS5830 评估模块
PSPICE-FOR-TI — PSpice® for TI 设计和仿真工具
借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
HTSSOP (DAD) | 32 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。