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TPS51200

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3A Sink/Source DDR Termination Regulator w/ VTTREF Buffered Reference for DDR2, DDR3, DDR3L and DDR4

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Data sheet

TPS51200

ACTIVE
Data sheet Order now

Product details

Product type DDR Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Product type DDR Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² (3 mm × 3 mm)
  • Input voltage: supports 2.5v rail and 3.3v rail
  • VLDOIN voltage range: 1.1V to 3.5V
  • Sink and source termination regulator includes droop compensation
  • Requires minimum output capacitance of 20µF (Typically 3 × 10µF MLCCs) for memory termination applications (DDR)
  • PGOOD to monitor output regulation
  • EN Input
  • REFIN input allows for flexible input tracking either directly or through resistor divider
  • Remote sensing (VOSNS)
  • ±10mA buffered reference (REFOUT)
  • Built-in soft start, UVLO, and OCL
  • Thermal shutdown
  • Supports DDR, DDR2, DDR3, DDR3L, low-power DDR3, and DDR4 VTT applications
  • 10-Pin VSON package with thermal pad
  • Input voltage: supports 2.5v rail and 3.3v rail
  • VLDOIN voltage range: 1.1V to 3.5V
  • Sink and source termination regulator includes droop compensation
  • Requires minimum output capacitance of 20µF (Typically 3 × 10µF MLCCs) for memory termination applications (DDR)
  • PGOOD to monitor output regulation
  • EN Input
  • REFIN input allows for flexible input tracking either directly or through resistor divider
  • Remote sensing (VOSNS)
  • ±10mA buffered reference (REFOUT)
  • Built-in soft start, UVLO, and OCL
  • Thermal shutdown
  • Supports DDR, DDR2, DDR3, DDR3L, low-power DDR3, and DDR4 VTT applications
  • 10-Pin VSON package with thermal pad

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.

The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20µF. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200 is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –40°C to +85°C.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet TPS51200 Sink and Source DDR Termination Regulator datasheet (Rev. E) PDF | HTML Sep 5, 2025
Application note LDO Noise Demystified (Rev. B) PDF | HTML Aug 18, 2020
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) Jul 9, 2020
Application note Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) PDF | HTML Jan 8, 2020
Selection guide Power Management Guide 2018 (Rev. R) Jun 25, 2018
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Application note Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) May 24, 2010
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr 28, 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices Apr 20, 2010
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White paper Spartan 6 LX150T Modular Solution Oct 14, 2009
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Design & development

Power-supply solutions

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Evaluation board

TPS51200EVM — TPS51200 Sink Source DDR Termination Regulator

The TPS51200EVM evaluation board, HPA322A is designed to evaluate the performance andcharacteristics of TI's cost optimized DDR/DDR2/DDR3/LP DDR3 VTT termination regulator, the TPS51200. The TPS51200 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR (...)

User guide: PDF
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Simulation model

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice model
Supported products & hardware
Simulation model

TPS51200 PSpice Transient Model (Rev. A)

SLVM068 (36 KB) - PSpice model
Supported products & hardware
Simulation model

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI reference design
Supported products & hardware
Simulation model

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice model
Supported products & hardware
Simulation model

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI reference design
Supported products & hardware
Simulation model

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice model
Supported products & hardware

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