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SN74LVC2G101-Q1

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Automotive two-channel 1.1V-to-3.6V configurable gate for clock input with Schmitt-trigger inputs

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Data sheet

SN74LVC2G101-Q1

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 2 Inputs per channel 1 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 2 Inputs per channel 1 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)

  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 7ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)

  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 7ns at 3.3V supply
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004

The SN74LVC2G101-Q1 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.

The SN74LVC2G101-Q1 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.
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* Data sheet SN74LVC2G101-Q1 Automotive Dual D-Type Flip-Flop with Configurable Multiple-Function Gated Clock datasheet PDF | HTML Jun 14, 2024

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TSSOP (PW) 16 Ultra Librarian
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