Down translation:
The SN74LV8T273 contains eight positive-edge-triggered D-type flip-flops with a direct active low clear ( CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV8T273 Translating Octal D-Type Flip-Flops with Clear datasheet | PDF | HTML | 01 Jul 2025 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
| VQFN (RKS) | 20 | Ultra Librarian |
| VSSOP (DGS) | 20 | Ultra Librarian |
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