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SN74LV164A

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Eight-bit parallel-out serial shift registers

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Data sheet

SN74LV164A

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 65 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 65 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm)
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 10.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Ioff supports live insertion, partial power-down mode, and back-drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250 mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 10.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Ioff supports live insertion, partial power-down mode, and back-drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation.

The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV164A 8-Bit Parallel-Out Serial Shift Registers datasheet (Rev. K) PDF | HTML Mar 24, 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022
Design guide EMC Compatible Automotive LED Rear Lamp Sequential-Turn Animation Design Guide Jun 2, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74LV164A IBIS Model

SCEM131.ZIP (16 KB) - IBIS model
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Reference design

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Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
WQFN (BQA) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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