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SN65LVDS4

ACTIVE

500-Mbps LVDS single high-speed receiver

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Data sheet

SN65LVDS4

ACTIVE
Data sheet Order now

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 500 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 1 Signaling rate (Mbps) 500 Input signal LVDS Output signal LVCMOS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
UQFN (RSE) 10 3 mm² (2 mm × 1.5 mm)
  • Designed for Signaling Rates(1) up to:
    • 500-Mbps Receiver
  • Operates From a 1.8-V or 2.5-V Core Supply
  • Available in 1.5-mm × 2-mm UQFN Package
  • Bus-Terminal ESD Exceeds 2 kV (HBM)
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV Into a 100-Ω Load
  • Propagation Delay Times
    • 2.1 ns Typical Receiver
  • Power Dissipation at 250 MHz
    • 40 mW Typical
  • Requires External Failsafe
  • Differential Input Voltage Threshold Less Than 50
    mV
  • Can Provide Output Voltage Logic Level (3.3-V
    LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
    on External VDD Pin, Thus Eliminating External
    LevelTranslation
  • Designed for Signaling Rates(1) up to:
    • 500-Mbps Receiver
  • Operates From a 1.8-V or 2.5-V Core Supply
  • Available in 1.5-mm × 2-mm UQFN Package
  • Bus-Terminal ESD Exceeds 2 kV (HBM)
  • Low-Voltage Differential Signaling With Typical
    Output Voltages of 350 mV Into a 100-Ω Load
  • Propagation Delay Times
    • 2.1 ns Typical Receiver
  • Power Dissipation at 250 MHz
    • 40 mW Typical
  • Requires External Failsafe
  • Differential Input Voltage Threshold Less Than 50
    mV
  • Can Provide Output Voltage Logic Level (3.3-V
    LVTTL, 2.5-V LVCMOS, 1.8-V LVCMOS) Based
    on External VDD Pin, Thus Eliminating External
    LevelTranslation

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.

The SN65LVDS4 is a single, low-voltage, differential line receiver in a small-outline UQFN package.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN65LVDS4 1.8-V High-Speed Differential Line Receiver datasheet (Rev. A) PDF | HTML Nov 30, 2015
Application brief Level Shift No More: Support Low Voltage I/O Signals into a FPGA, Processor, or ASIC (Rev. A) PDF | HTML Aug 15, 2024
Application brief How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver Jan 9, 2019
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter Dec 28, 2018
Application brief LVDS to Improve EMC in Motor Drives Sep 27, 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug 3, 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018
Application note TMDS Clock Detection Solution in HDMI Sink Applications PDF | HTML Aug 23, 2017
Technical article Get Connected: High-speed LVDS comparator PDF | HTML Jun 3, 2015

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