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SN54AHC273

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Octal D-type Flip-Flops With Clear

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Data sheet

SN54AHC273

LAST TIME BUY
Data sheet Order now

Product details

Number of channels 8 Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

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* Data sheet SNx4AHC273 Octal D-Type Flip-Flops With Clear datasheet (Rev. J) PDF | HTML 23 Jul 2024

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