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The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LP2995 DDR Termination Regulator datasheet (Rev. M) | Mar 19, 2013 | |
| Application note | Limiting DDR Termination Regulators’ Inrush Current | Aug 23, 2016 | ||
| Application note | AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) | May 6, 2013 | ||
| Application note | DDR-SDRAM Termination Simplified Using A Linear Regulator | Jul 23, 2002 |
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WQFN (NHP) | 16 | Ultra Librarian |
| HSOIC (DDA) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
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