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CDCP1803

ACTIVE

1:3 LVPECL clock buffer with programable divider

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Data sheet

CDCP1803

ACTIVE
Data sheet Order now

Product details

Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 15 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVPECL
VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
  • Programmable Output Divider for Two LVPECL Outputs
  • Low-Output Skew 15 ps (Typical)
  • VCC Range 3 V–3.6 V
  • Signaling Rate Up to 800-MHz LVPECL
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling:
    LVDS, HSTL, CML, VML, SSTL-2, and
    Single-Ended: LVTTL/LVCMOS
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
  • Programmable Output Divider for Two LVPECL Outputs
  • Low-Output Skew 15 ps (Typical)
  • VCC Range 3 V–3.6 V
  • Signaling Rate Up to 800-MHz LVPECL
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling:
    LVDS, HSTL, CML, VML, SSTL-2, and
    Single-Ended: LVTTL/LVCMOS

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 1:3 LVPECL Clock Buffer with Programmable Divider, CDCP1803 datasheet (Rev. F) Dec 4, 2013
Application note Dual Purposes: Data Buffer, The Other Face of CDCP1803 Aug 13, 2004

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Simulation model

CDCP1803 IBIS Model (Rev. B)

SCAC048 (56 KB) - IBIS model
Supported products & hardware
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VQFN (RGE) 24 Ultra Librarian
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