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CD74HC273

ACTIVE

High Speed CMOS Logic Octal D-Type Flip-Flops with Reset

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Data sheet

CD74HC273

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family HC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 23 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 8 Technology family HC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 23 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Common clock and asynchronous controller reset
  • Positive edge triggering
  • Buffered inputs
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types:
    • 2V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • 4.5V to 5.5V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1µA at VOL,VOH
  • Common clock and asynchronous controller reset
  • Positive edge triggering
  • Buffered inputs
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types:
    • 2V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT types:
    • 4.5V to 5.5V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
    • CMOS input compatibility, II ≤ 1µA at VOL,VOH

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.

The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.

Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset datasheet (Rev. D) PDF | HTML Oct 28, 2025
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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SOIC (DW) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian
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