SN74AHC273

ACTIVE

Octal D-Type Flip-Flops With Clear

Product details

Number of channels 8 Technology family AHC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 8 Technology family AHC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 110 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs Operating temperature range (°C) -40 to 125 Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm) VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm)
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Operating range 2V to 5.5V VCC
  • Contain eight flip-flops with single-rail outputs
  • Direct clear input
  • Individual data input to each flip-flop
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • On products compliant to MIL-PRF-38535, All parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4AHC273 Octal D-Type Flip-Flops With Clear datasheet (Rev. J) PDF | HTML Jul 23, 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
VQFN (RKS) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian

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