Calculation tool
ADC12DJ5200RF-CALC — ADC12DJ5200RF input network full-scale calculation tool.
Calculation tool referenced in application note SLVAFZ7.
ADC12DJ5200-SP
Radiation-hardness-assured (RHA), 300-krad, 12-bit, dual 5.2-GSPS or single 10.4-GSPS ADC
Data sheet
ADC12DJ5200-SP
- Radiation Tolerance:
- Total Ionizing Dose (TID): 300krad (Si)
- Single Event Latchup (SEL): 120MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- ADC core:
- 12-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Dual-channel mode: –151.8dBFS/Hz
- Single-channel mode: –154.4dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Time stamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4W
- Power supplies: 1.1V, 1.9V
The ADC12DJ5200-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ5200-SP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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Technical documentation
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View all 4 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC12DJ5200-SP 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) | PDF | HTML | 08 Apr 2025 |
| * | Radiation & reliability report | ADC12DJ5200-SHP Production Flow and Reliability Report | 10 Mar 2025 | |
| Application brief | DLA Approved Optimizations for QML Products (Rev. B) | PDF | HTML | 23 Oct 2024 | |
| Technical article | How SHP in plastic packaging addresses 3 key space application design challenges | PDF | HTML | 17 Oct 2022 |
Design & development
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Evaluation board
ADC12DJ5200RFEVM — ADC12DJ5200RF RF-sampling 12-bit dual 5.2GSPS or single 10.4GSPS ADC evaluation module
The ADC12DJ5200RF evaluation module (EVM) is designed to evaluate the ADC12DJ5200RF family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ5200RF, a 12-bit, dual-channel 5.2GSPS or single-channel 10.4GSPS ADC with JESD204B interface and allows for evaluation (...)
Simulation model
ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)
SLVMD65A.ZIP (49879 KB) - IBIS-AMI Model
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (ALR) | 144 | Ultra Librarian |
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