SN74LV8T373-EP
- Wide operating range of 1.65V to 5.5V
- 5.5V tolerant input pins
- Single-supply voltage
translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
- 1.2V to 1.8V
- 1.5V to 2.5V
- 1.8V to 3.3V
- 3.3V to 5.0V
-
Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
- Up translation:
- Up to 150Mbps with 5V or 3.3V VCC
- Supports standard function pinout
- Latch-up performance exceeds 250mAper JESD 17
- Supports defense and aerospace applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
The SN74LV8T373-EP device is an octal transparent D-type latch designed for 2V to 5.5V VCC operation.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV8T373-EP Enhanced Product Octal Transparent D-Type Latches with 3-State Outputs datasheet (Rev. A) | PDF | HTML | 2024/10/23 | ||
| * | 輻射及可靠性報告 | SN74LV8T373-EP Enhanced Product Qualification and Reliability Report | PDF | HTML | 2024/10/9 |
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |