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移位暫存器

SN74LV595A-Q1

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產品規格表

SN74LV595A-Q1

現行
產品規格表 立即訂購

產品詳細資料

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (MHz) 75 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 40 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (MHz) 75 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 40 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • Qualified for automotive applications
  • Available in wettable flank QFN (WBQB) package
  • Customer-specific configuration control can be supported along with major-change approval
  • 2-V to 5.5-V V CC operation
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Supports mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift
  • I off supports partial-power-down mode operation
  • Shift register has direct clear
  • Qualified for automotive applications
  • Available in wettable flank QFN (WBQB) package
  • Customer-specific configuration control can be supported along with major-change approval
  • 2-V to 5.5-V V CC operation
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Supports mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift
  • I off supports partial-power-down mode operation
  • Shift register has direct clear

The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.

The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.

The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LV595A-Q1 8-Bit Shift Registers With 3-State Output Registers datasheet (Rev. G) PDF | HTML 2023/3/24
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
更多文件說明 Automotive Logic Devices Brochure 2014/8/27

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模擬型號

SN74LV595A IBIS Model (Rev. C)

SCEM148C.ZIP (45 KB) - IBIS 模型
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TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
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