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電壓轉換器及電平移位器
電壓轉換器

SN74LV4T125-EP

現行
立即訂購
產品規格表

SN74LV4T125-EP

現行
產品規格表 立即訂購

產品詳細資料

Bits (#) 4 Data rate (max) (Mbps) 150 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.6 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Over-voltage tolerant inputs, Single supply Prop delay (ns) 10.2 Technology family LVxT Supply current (max) (mA) 0.02 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Bits (#) 4 Data rate (max) (Mbps) 150 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.6 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Over-voltage tolerant inputs, Single supply Prop delay (ns) 10.2 Technology family LVxT Supply current (max) (mA) 0.02 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • Wide operating range of 1.8V to 5.5V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mA per JESD 17
  • Wide operating range of 1.8V to 5.5V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2V to 1.8V

      • 1.5V to 2.5V

      • 1.8V to 3.3V

      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mA per JESD 17

The SN74LV4T125-EP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV4T125-EP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet PDF | HTML 2024/1/31
* 輻射及可靠性報告 SN74LV4T125-EP Enhanced Product Qualification and Reliability Report PDF | HTML 2024/3/8
應用說明 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/2
應用說明 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/7/12
應用說明 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/7/3

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