SN74LV273A-Q1
- AEC-Q100 qualified for automotive applications:
- Device temperature grade 1:
- 40°C to +125°C, TA
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C6
- Device temperature grade 1:
- Available in wettable flank QFN (WRKS) package
- 2V to 5.5V VCC operation
- Maximum tpd of 10.5ns at 5V
- Supports mixed-mode voltage operation on all ports
- Ioff supports partial power-down mode operation
- Latch-up performance exceeds 250mA per JESD 17
The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low clear (CLR) input and clock (CLK).
Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q) outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV273A-Q1 Automotive Octal D-Type Flip-Flops With Clear datasheet (Rev. C) | PDF | HTML | 2026/6/2 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組
14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用於支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGS) | 20 | Ultra Librarian |
| VQFN (RKS) | 20 | Ultra Librarian |