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SN74LXC1T14

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Single-channel fixed direction inverting 1.1-V to 5.5-V voltage level translator

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Data sheet

SN74LXC1T14

ACTIVE
Data sheet Order now

Product details

Bits (#) 1 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO Features Integrated pulldown resistors, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 8 Technology family LXC Supply current (max) (mA) 0.0055 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 1 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Fixed-direction Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO Features Integrated pulldown resistors, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 8 Technology family LXC Supply current (max) (mA) 0.0055 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • Input with integrated dynamic pull-down resistors help reduce external component count
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption
    • 3-µA maximum (25°C)
    • 6-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/O’s get pulled-down and then become high-impedance
  • Overvoltage tolerant inputs accept voltages up to 5.5 V regardless of supply voltage.
  • Ioff supports partial-power-down mode operation
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V human-body model
    • 1000-V charged-device model
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • Input with integrated dynamic pull-down resistors help reduce external component count
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption
    • 3-µA maximum (25°C)
    • 6-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/O’s get pulled-down and then become high-impedance
  • Overvoltage tolerant inputs accept voltages up to 5.5 V regardless of supply voltage.
  • Ioff supports partial-power-down mode operation
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V human-body model
    • 1000-V charged-device model

The SN74LXC1T14 is a single bit, dual-supply inverting voltage level translation device with Schmitt-trigger input. The input pin A is referenced to VCCI logic levels, and output pin Y is referenced to VCCO logic levels. The input pin A is able to accept voltages ranging from 1.1 V to 5.5 V and can be connected directly to VCCI or GND. See Device Functional Modes for a summary of the operation of the logic.

This device ensures low power consumption and is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The SN74LXC1T14 is a single bit, dual-supply inverting voltage level translation device with Schmitt-trigger input. The input pin A is referenced to VCCI logic levels, and output pin Y is referenced to VCCO logic levels. The input pin A is able to accept voltages ranging from 1.1 V to 5.5 V and can be connected directly to VCCI or GND. See Device Functional Modes for a summary of the operation of the logic.

This device ensures low power consumption and is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LXC1T14 Dual-Supply Inverting Translator with Schmitt-Trigger Input datasheet PDF | HTML 10 May 2022
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74LXC1T14 IBIS Model

SCEM794.ZIP (56 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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