Home Logic & voltage translation Flip-flops, latches & registers D-type flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
D-type flip-flops

SN74LVC2G74

ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Order now
Data sheet

SN74LVC2G74

ACTIVE
Data sheet Order now

Product details

Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 200 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 200 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • Maximum tpd of 5.9 ns at 3.3 V
  • Low power consumption, 10 µA maximum ICC
  • ±24 mA output drive at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000 V human-body model
    • 200 V machine model
    • 1000 V charged-device model
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • Maximum tpd of 5.9 ns at 3.3 V
  • Low power consumption, 10 µA maximum ICC
  • ±24 mA output drive at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000 V human-body model
    • 200 V machine model
    • 1000 V charged-device model

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter Find other D-type flip-flops
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device.
SN74AUP1G74 ACTIVE Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
Similar functionality to the compared device.
SN74AHC74 ACTIVE Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA

Technical documentation

No results found. Please clear your search and try again.
View all 4
Top documentation Type Title Format options Date
* Data sheet SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. Q) PDF | HTML Sep 14, 2021
Product overview Generate a Timed Pulse Using a Binary Counter PDF | HTML Jun 14, 2023
Product overview Generate an Enable Signal that can be Toggled PDF | HTML Jun 14, 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Simulation model

HSPICE MODEL OF SN74LVC2G74

SCEJ238.ZIP (91 KB) - HSpice model
Supported products & hardware
Simulation model

SN74LVC2G74 IBIS Model

SCEM282.ZIP (51 KB) - IBIS model
Supported products & hardware
Reference design

TIDA-010032 — Universal data concentrator reference design supporting Ethernet, 6LoWPAN RF mesh & more

IPv6-based grid communications are becoming the standard choice in industrial markets and applications like smart meters and grid automation. The universal data concentrator design provides a complete IPv6-based network solution integrated with Ethernet backbone communication, 6LoWPAN RF mesh (...)

Supported products & hardware
Reference design

TIDA-010237 — AC and DC current fault detection reference design

This reference design detects mA-level AC and DC ground fault currents. An auto-oscillation circuit is implemented using a DRV8220 H-bridge that drives the magnetic core in and out of saturation. In addition, an active filter circuit is implemented to identify fault current signal and level.
Supported products & hardware
Reference design

TIDM-02000 — Peak current-mode controlled phase-shifted full-bridge reference design using C2000™ real-time MCU

This design implements a digitally peak current mode controlled (PCMC) phase shifted full bridge (PSFB) DC-DC converter which converts a 400-V DC input to a regulated 12-V DC output. Novel PCMC waveform generation based on type-4 PWM and internal slope compensation, and simple PCMC implementation (...)
Supported products & hardware
Reference design

TIDM-BIDIR-400-12 — Bidirectional 400-V/12-V DC/DC Converter Reference Design

The Bidirectional 400V-12V DC/DC Converter Reference Design is a microcontroller-based implementation of an isolated bi-directional DC-DC converter.  A phase shifted full-bridge (PSFB) with synchronous rectification controls power flow from a 400V bus/battery to the 12V battery in step-down (...)

Supported products & hardware
Reference design

TIDM-SOLAR-DCDC — C2000™ MCU solar DC/DC converter with Maximum Power Point Tracking (MPPT) reference design

This design is a digitally-controlled, solar DC/DC converter with maximum power point tracking (MPPT), for use in central or string solar inverters. The design acts as a front-end MPPT DC/DC converter for the TIDM-SOLAR-ONEPHINV, a grid-tied, single phase, DC/AC inverter. Together, they form a (...)

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VSSOP (DCU) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos