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Inverting buffers & drivers

SN74LVC06A

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6-ch, 1.65-V to 3.6-V inverters with open-drain outputs

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Data sheet

SN74LVC06A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) 0 Supply current (max) (µA) 40 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) 0 Supply current (max) (µA) 40 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm)
  • Operate From 1.65 V to 3.6 V
  • Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
  • Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V
  • Max tpd of 3.7 ns at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Operate From 1.65 V to 3.6 V
  • Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
  • Inputs and Open-Drain Outputs Accept Voltages up to 5.5 V
  • Max tpd of 3.7 ns at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

These hex inverter buffers/drivers are designed for 1.65-V to 3.6-V VCC operation.

The outputs of the 'LVC06A devices are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

These hex inverter buffers/drivers are designed for 1.65-V to 3.6-V VCC operation.

The outputs of the 'LVC06A devices are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN54LVC06A, SN74LVC06A datasheet (Rev. N) Jul 26, 2005
Application note LVC07A: Applications Of An Open-Drain Hex Buffer And Discussion Of Char Results Apr 8, 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

HSPICE Model for SN74LVC06A

SCEJ243.ZIP (95 KB) - HSpice model
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Simulation model

SN74LVC06A Behavioral SPICE Model

SCAM115.ZIP (7 KB) - PSpice model
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Simulation model

SN74LVC06A IBIS Model (Rev. A)

SCEM156 (24 KB) - IBIS model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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