SN74LV8T165-Q1

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Automotive, 1.65 V to 5 V parallel-load eight-channel shift register with logic level shifter

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Data sheet

document-pdfAcrobat SN74LV8T165-Q1Automotive Parallel-Load 8-Bit Shift Registers datasheet (Rev. A) PDF | HTML

SN74LV8T165-Q1

ACTIVE

Data sheet

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Product details

Technology family

LVxT

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

100

IOH (max) (mA)

-8

IOL (max) (mA)

8

Features

Balanced outputs, Single supply, Voltage translation

Input type

TTL-Compatible CMOS

Output type

Balanced CMOS

Operating temperature range (°C)

-40 to 125

Technology family

LVxT

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

100

IOH (max) (mA)

-8

IOL (max) (mA)

8

Features

Balanced outputs, Single supply, Voltage translation

Input type

TTL-Compatible CMOS

Output type

Balanced CMOS

Operating temperature range (°C)

-40 to 125

TSSOP (PW)

16

32 mm² (5 mm × 6.4 mm)

WQFN (BQB)

16

8.75 mm² (3.5 mm × 2.5 mm)

Wide operating range of 1.8 V to 5.5 V
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2 V to 1.8 V
  - 1.5 V to 2.5 V
  - 1.8 V to 3.3 V
  - 3.3 V to 5.0 V
- Down translation:
  - 5.0 V, 3.3 V, 2.5 V to 1.8 V
  - 5.0 V, 3.3 V to 2.5 V
  - 5.0 V to 3.3 V
5.5 V tolerant input pins
Supports standard pinouts
Up to 150Mbps with 5 V or 3.3 V V CC
Latching logic with known power-up state
Latch-up performance exceeds 250 mA per JESD 17

Wide operating range of 1.8 V to 5.5 V
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2 V to 1.8 V
  - 1.5 V to 2.5 V
  - 1.8 V to 3.3 V
  - 3.3 V to 5.0 V
- Down translation:
  - 5.0 V, 3.3 V, 2.5 V to 1.8 V
  - 5.0 V, 3.3 V to 2.5 V
  - 5.0 V to 3.3 V
5.5 V tolerant input pins
Supports standard pinouts
Up to 150Mbps with 5 V or 3.3 V V CC
Latching logic with known power-up state
Latch-up performance exceeds 250 mA per JESD 17

The SN74LV8T165-Q1 device is a parallel- or serial-in, serial-out 8-bit shift register. This device has two modes of operation: load data, and shift data which are controlled by the SH/ LD input. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

The SN74LV8T165-Q1 device is a parallel- or serial-in, serial-out 8-bit shift register. This device has two modes of operation: load data, and shift data which are controlled by the SH/ LD input. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

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Technical documentation

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Top documentation	Type	Title	Format options	Date
*	Data sheet	SN74LV8T165-Q1Automotive Parallel-Load 8-Bit Shift Registers datasheet (Rev. A)	PDF \| HTML	Nov 3, 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML

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Simulation model