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SN74LV595A

ACTIVE

Eight-bit shift registers with 3-state output registers

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Data sheet

SN74LV595A

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (MHz) 95 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (MHz) 95 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) VQFN (RGY) 16 14 mm² (4 mm × 3.5 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 7.1 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift
  • I off supports live insertion, partial power-down mode, and back-drive protection
  • Shift register has direct clear
  • Latch-up performance exceeds 250 mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 7.1 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • 8-bit serial-in, parallel-out shift
  • I off supports live insertion, partial power-down mode, and back-drive protection
  • Shift register has direct clear
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV595A device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered.

The SN74LV595A device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV595A 8-Bit Shift Registers With 3-State Output Registers datasheet (Rev. T) PDF | HTML Mar 24, 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74LV595A IBIS Model (Rev. C)

SCEM148C.ZIP (45 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
VQFN (RGY) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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