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SN74LV573A

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Octal Transparent D-Type Latches With 3-State Outputs

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Data sheet

SN74LV573A

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family LV-A Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 20 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) VQFN (RGY) 20 15.75 mm² (4.5 mm × 3.5 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm)
  • V CC operation of 2 V to 5.5 V
  • Max t pd of 8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) latch-up performance exceeds 250 mA per <0.8 V at V CC = 3.3 V , T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Max t pd of 8 ns at 5 V
  • Typical V OLP (Output Ground Bounce) latch-up performance exceeds 250 mA per <0.8 V at V CC = 3.3 V , T A = 25°C
  • Typical V OHV (Output V OH Undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV573A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. J) PDF | HTML Mar 23, 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74LV573A IBIS Model

SCEM145.ZIP (17 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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