SN74LV27A

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3-ch, 3-input, 2-V to 5.5-V NOR gates

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Data sheet

document-pdfAcrobat SN74LV27A Triple 3-Input Positive-NOR Gate datasheet (Rev. F) PDF | HTML

SN74LV27A

ACTIVE

Data sheet

Order now

Product details

Technology family

LV-A

Number of channels

3

Inputs per channel

3

IOL (max) (mA)

12

IOH (max) (mA)

-12

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

70

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

LV-A

Number of channels

3

Inputs per channel

3

IOL (max) (mA)

12

IOH (max) (mA)

-12

Output type

Push-Pull

Input type

Standard CMOS

Features

Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

70

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

SSOP (DB)

14

48.36 mm² (6.2 mm × 7.8 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

TVSOP (DGV)

14

23.04 mm² (3.6 mm × 6.4 mm)

Operation of 2-V to 5.5-V V CC
Max t pd of 7 ns at 5 V
Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
I off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Operation of 2-V to 5.5-V V CC
Max t pd of 7 ns at 5 V
Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
Typical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°C
I off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V V CC operation.

The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic.

These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Top documentation	Type	Title	Format options	Date
*	Data sheet	SN74LV27A Triple 3-Input Positive-NOR Gate datasheet (Rev. F)	PDF \| HTML	Jul 14, 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML

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Simulation model