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SN74LV175A

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Quadruple D-Type Flip-Flops With Clear

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Data sheet

SN74LV175A

ACTIVE
Data sheet Order now

Product details

Number of channels 4 Technology family LV-A Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 4 Technology family LV-A Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 70 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
TVSOP (DGV) 16 23.04 mm² (3.6 mm × 6.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm)
  • V CC operation of 2 V to 5.5
  • Maximum t pd of 7.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • I off supports partial-power-down mode operation
  • Supports mixed-mode voltage operation on all ports
  • Contains four flip-flops with double-rail outputs
  • V CC operation of 2 V to 5.5
  • Maximum t pd of 7.5 ns at 5 V
  • Typical V OLP (output ground bounce) < 0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) > 2.3 V at V CC = 3.3 V, T A = 25°C
  • I off supports partial-power-down mode operation
  • Supports mixed-mode voltage operation on all ports
  • Contains four flip-flops with double-rail outputs

The SN74LV175A device is quadruple D-type flip-flops designed for 2 V to 5.5 V V CC operation. These devices have a direct clear ( CLR) input and feature complementary outputs from each flip-flop.

The SN74LV175A device is quadruple D-type flip-flops designed for 2 V to 5.5 V V CC operation. These devices have a direct clear ( CLR) input and feature complementary outputs from each flip-flop.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV175A Quadruple D-Type Flip-Flops With Clear datasheet (Rev. J) PDF | HTML Mar 23, 2023
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Simulation model

SN74LV175A IBIS Model

SCEM134.ZIP (16 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TVSOP (DGV) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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