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SN74HC259

ACTIVE

8-Bit Addressable Latches

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Data sheet

SN74HC259

ACTIVE
Data sheet Order now

Product details

Function Addressable latch Number of channels 8 Technology family HC Input type Standard CMOS Output type Push-Pull Data rate (max) (Mbps) 56 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Partial power down (Ioff), Standard speed (tpd > 50ns), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Function Addressable latch Number of channels 8 Technology family HC Input type Standard CMOS Output type Push-Pull Data rate (max) (Mbps) 56 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Partial power down (Ioff), Standard speed (tpd > 50ns), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOT-23-THN (DYY) 16 8.4 mm² (4.2 mm × 2 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4HC259 8-Bit Addressable Latches datasheet (Rev. F) PDF | HTML Mar 16, 2022
Application brief Using Linear Interpolation to Estimate Specification Values PDF | HTML Apr 13, 2026
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOT-23-THN (DYY) 16 Ultra Librarian
PDIP (N) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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