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SN74CBT3126

ACTIVE

5-V, 1:1 (SPST), 4-channel general-purpose FET bus switch with st&ard '126-type pinout

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Data sheet

SN74CBT3126

ACTIVE
Data sheet Order now

Product details

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 5.5 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 22000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 5.5 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 22000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SOIC (D) 14 51.9 mm² 8.65 x 6 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 SSOP (DBQ) 16 29.4 mm² 4.9 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • Standard ’126-Type Pinout (D, DB, DGV, and PW Packages)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Standard ’126-Type Pinout (D, DB, DGV, and PW Packages)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
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* Data sheet SN74CBT3126 datasheet (Rev. K) 06 Oct 2003

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