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SN74AUP1G79

ACTIVE

Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

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Data sheet

SN74AUP1G79

ACTIVE
Data sheet Order now

Product details

Number of channels 1 Technology family AUP Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 260 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 1 Technology family AUP Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 260 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 3 pF Typical at 3.3 V
  • Low Input Capacitance:
    Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    < 10% of VCC
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 3 pF Typical at 3.3 V
  • Low Input Capacitance:
    Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    < 10% of VCC
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.

The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.

The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. I) PDF | HTML Sep 6, 2017
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
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Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

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Simulation model

SN74AUP1G79 IBIS Model (Rev. B)

SCEM442B.ZIP (65 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
USON (DRY) 6 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
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