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XOR (exclusive OR) gates

SN74AHCT86

ACTIVE

4-ch, 2-input, 4.5-V to 5.5-V XOR (exclusive OR) gates with TTL-compatible CMOS inputs

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Data sheet

SN74AHCT86

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Number of channels 4 Inputs per channel 2 IOL (max) (mA) 8 Input type TTL-Compatible CMOS IOH (max) (mA) -8 Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHCT Number of channels 4 Inputs per channel 2 IOL (max) (mA) 8 Input type TTL-Compatible CMOS IOH (max) (mA) -8 Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm)
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The SNx4AHCT86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A × B or Y = AB + A B in positive logic.

The SNx4AHCT86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A × B or Y = AB + A B in positive logic.
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SN74ACT86 ACTIVE 4-ch, 2-input, 4.5-V to 5.5-V XOR (exclusive OR) gates with TTL-compatible CMOS inputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

Technical documentation

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* Data sheet SNx4AHCT86 Quadruple 2-Input Exclusive-OR Gates datasheet (Rev. P) PDF | HTML Oct 17, 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74AHCT86 Behavioral SPICE Model

SCLM238.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74AHCT86 IBIS Model

SCLM064.ZIP (13 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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