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SN74AHCT374

ACTIVE

Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs

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Data sheet

SN74AHCT374

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm)
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 10.5ns (5V VCC at CL = 15pF)
  • Supports 75MHz
  • Latch-up performance exceeds 250mAper JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 10.5ns (5V VCC at CL = 15pF)
  • Supports 75MHz
  • Latch-up performance exceeds 250mAper JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SNx4AHCT374 contains eight D-type flip-flops. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The SNx4AHCT374 contains eight D-type flip-flops. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.
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SN74ACT374 ACTIVE Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
CD74ACT374 ACTIVE Octal D-Type Flip-Flops with 3-State Outputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
Similar functionality to the compared device.
CD74HCT374 ACTIVE High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SNx4AHCT374 Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs datasheet (Rev. O) PDF | HTML Jul 24, 2025
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Simulation model

SN74AHCT374 IBIS Model

SCLM074.ZIP (17 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
VQFN (RKS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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