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SN74AHCT132

ACTIVE

4-ch, 4-input, 4.5-V to 5.5-V NAND gates with Schmitt-Trigger inputs

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Data sheet

SN74AHCT132

ACTIVE
Data sheet Order now

Product details

Technology family AHCT Number of channels 4 Inputs per channel 4 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AHCT Number of channels 4 Inputs per channel 4 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • Operating range of 4.5 V to 5.5 V
  • Low power consumption, 10-µA maximum I CC
  • ±8-mA output drive at 5 V
  • Operation from very slow input transitions
  • Temperature-compensated threshold levels
  • High noise immunity
  • Same pinouts as ’AHCT00
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating range of 4.5 V to 5.5 V
  • Low power consumption, 10-µA maximum I CC
  • ±8-mA output drive at 5 V
  • Operation from very slow input transitions
  • Temperature-compensated threshold levels
  • High noise immunity
  • Same pinouts as ’AHCT00
  • Latch-up performance exceeds 250 mA per JESD 17

The ’AHCT132 devices are quadruple positive-NAND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

The ’AHCT132 devices are quadruple positive-NAND gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
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NEW SN74ACT132 ACTIVE 4-ch, 4-input NAND gate with TTL compatible inputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
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Technical documentation

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* Data sheet SN54AHCT132, SN74AHCT132 Quadruple Positive-NAND GatesWith Schmitt-trigger Inputs datasheet (Rev. I) PDF | HTML Oct 16, 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Simulation model

SN74AHCT132 Behavioral SPICE Model

SCLM254.ZIP (7 KB) - PSpice model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
PDIP (N) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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