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SN74ACT595

ACTIVE

8-bit shift register with 3-state output register

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Data sheet

SN74ACT595

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in Bits (#) 8 Technology family ACT Input type CMOS Output type 3-State Clock frequency (MHz) 92 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in Bits (#) 8 Technology family ACT Input type CMOS Output type 3-State Clock frequency (MHz) 92 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.9ns max
  • Operating voltage range of 4.5V to 5.5V
  • TTL-compatible inputs
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Fast operation with delay of 11.9ns max

The SN74ACT595 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the register outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.

The SN74ACT595 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the register outputs are in a high-impedance state. Internal register data is not impacted by the operation of the OE input.
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* Data sheet SN74ACT595 8-Bit Shift Register With TTL-Compatible Inputs And Output Registers datasheet PDF | HTML Nov 6, 2024

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
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