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CY74FCT574T

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Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs

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Data sheet
User guides

CY74FCT574T

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm)
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate
  • CY54FCT574T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT574T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate
  • CY54FCT574T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT574T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current
  • 3-State Outputs

The \x92FCT574T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The \x92FCT574T are identical to \x92FCT374T, except for a flow-through pinout to simplify board design. The eight flip-flops in the \x92FCT574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT574T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The \x92FCT574T are identical to \x92FCT374T, except for a flow-through pinout to simplify board design. The eight flip-flops in the \x92FCT574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet 8-Bit Registers With 3-State Outputs datasheet Oct 11, 2001
* User guide CYFCT Parameter Measurement Information Apr 2, 2001
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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